Composable Silicon: An Autonomous Multi-Agent Workforce for Chip Design

The short version

For four decades, EDA automated the engineering algorithms of optimization and analysis. Frontier AI has now made the engineering tasks themselves automatable — so the durable advantage shifts to the continuously-improving engineering workflows that determine quality, productivity, and time-to-market. This is a detailed look at one such workflow: an end-to-end, long-running, fully autonomous multi-agent workforce that takes a chip from specification to sign-off-clean layout, and sharpens its own decisions as it goes.

That distinction matters because the world's appetite for custom silicon has become insatiable, and it is no longer concentrated in one place. At the edge, billions of sensors, phones, wearables, and vehicles demand on-device inference inside a power budget measured in milliwatts. In the data center, training and serving clusters consume megawatts and are bottlenecked not by ideas but by how fast accelerators, memory controllers, and interconnect fabrics can be designed, verified, and taped out. Across the explosion of AI inference applications — recommendation, vision, speech, generative models — every workload wants its own datapath, its own numeric format, its own energy-per-inference sweet spot. The demand curve is vertical; the supply of expert design teams is flat.

What makes the workforce autonomous

Four properties do the heavy lifting, and none of them are specific to processors:

Running that flow is a different matter: because it co-optimizes RTL authoring, design verification, physical implementation, and PPA closure as self-learning feedback loops — a verification failure rewriting the RTL and re-proving it, a physical-design bottleneck reaching back to change the microarchitecture and re-verify it, a power result reshaping the floorplan — a full closure runs unattended for hours to days, each loop governed by an enforced iteration budget and feeding the knowledge base so the system sharpens as it goes.

An end-to-end spec-to-GDS workflow

The design the workflow produced — we call it AgentCore — is a compact, 32-bit embedded-class processor built on an open, royalty-free instruction-set architecture. Its instruction set covers the base integer operations — arithmetic, logic, loads and stores, branches and jumps — extended with a hardware integer-multiply subset and a control-and-status-register interface for performance monitoring; it deliberately omits heavier facilities such as hardware divide, floating-point, and vector units to keep the design small and legible. Microarchitecturally it is a single-issue, in-order, multi-stage pipeline: instructions flow through the fetch, decode, execute, memory, and write-back phases one at a time, with full forwarding and hazard interlocks so that a sustained throughput close to one instruction per cycle is achievable. The pipeline depth itself is treated as a tunable design constraint rather than a fixed given — the flow can sweep stage count as one of its microarchitectural optimization axes, trading pipeline-fill latency against achievable frequency to maximize useful work per watt, then settle on the depth that best serves the XLOPS/W objective. The architectural register state lives in a flip-flop-based register file with asynchronous read and synchronous write, and the core talks to the outside world through separate 32-bit instruction and data memory ports clocked by a single clock with a synchronous, active-low reset.

The one piece of genuinely new RTL

The one genuinely new piece of RTL in this project was a dedicated control-and-status-register module implementing the XLOPS performance-counter ABI. It exposes eleven 64-bit free-running counters — nine per-op-class counters plus a cycle counter and a retired-instruction counter — that increment on each instruction retire, classified by op-class. On an integer-plus-multiply core only two of the nine work-classes are ever live (the INT32 multiply-accumulate class, and the memory class for loads and stores), plus the active-cycle denominator; the other six are tied to zero but present so the ABI is complete and forward-compatible with future floating-point and vector extensions.

A customizable objective

The objective for this run was XLOPS per watt. XLOPS is a generalized unit of useful work that superset-includes floating-point FLOPS, integer TOPS, and SIMD throughput: each retired operation is weighted by a factor that tracks its relative transistor cost, anchored so that one FP32 fused-multiply-add equals 1.0 (an INT32 MAC is 0.5, a memory op is 0.1, and so on across nine op-classes). Formally:

XLOPS aggregates work-weighted retired operations scaled by clock frequency; dividing by total power gives the efficiency figure of merit.

A five-sub-system, hierarchical flow

To pursue the objective, the workflow was composed as five cooperating sub-systems under a top-level orchestrator. Each sub-system owns a coherent slice of the design problem and hands a validated artifact bundle to the next; the forward path is linear, while the self-learning feedback edges (re-implement, re-verify, re-close) connect them back into loops.

Each sub-system runs its own bounded, self-learning iteration loop, and a central iteration-budget ledger is the canonical record of how many iterations each consumed — the governance that keeps long-horizon autonomy convergent rather than open-ended.

RTL and design verification

The Front-End sub-system turned the specification and the XLOPS/W objective into synthesizable RTL, and the Design Verification sub-system proved it correct against a golden ISA reference before a single gate was synthesized. Correctness here is binary and unforgiving: the device-under-test must reproduce the reference's full instruction-retire stream bit-for-bit, and the performance counters that feed the objective must themselves be validated against an independent classifier.

The functional suite passed bit-exact on the first pass, so the root-cause-analysis repair loop was never entered — 0 of its 8-iteration budget.

Physical design, PPA closure and sign-off

The Back-End sub-system carried the verified RTL through synthesis, placement, and routing, spending 9 of a 12-iteration PPA budget searching for XLOPS/W.

The optimization loop

Each iteration perturbed one of four axes — microarchitecture, back-end placement knobs, standard-cell threshold-voltage flavor, and the timing constraint — and re-scored the result on a self-consistent XLOPS/W basis (power measured at the same operating point as throughput, never at a slow clock that would inflate the number). The threshold-voltage and constraint sweeps confirmed that the standard-Vt library at the natural operating point was the genuine sweet spot for the objective — higher-frequency flavors existed but cost more power than they returned.

Sign-off

The routed design closed with zero routing DRC errors, zero antenna violations, and 100% routing completion — clearing the DRC-fix loop in 0 of 15 iterations and reaching a PASS-WITH-LIBRARY-WAIVERS sign-off.

Two of the three governed loops in the back half of the flow — RCA repair and DRC fix — consumed zero iterations. The design arrived at each gate already clean; the budget existed to absorb trouble that never came.

Amber = iterations spent searching · green = budget left untouched because the stage passed clean on entry.

Performance trajectory, end-to-end

What this trajectory captures is autonomy with a purpose. The agents were not following a fixed recipe; at each step the workflow chose what to change next — a placement-density sweep here, a microarchitectural edit there — measured the effect on the objective, learned from it, and decided where to push next. Crucially, the cross-stage edges are doing real work: when the physical-design loop reached back to alter the microarchitecture, the workflow automatically re-authored the RTL and re-ran the full verification suite before banking the gain. That closed-loop behavior — propose, implement, verify, measure, repeat — is what lets an autonomous workforce co-optimize a task that would otherwise demand a coordinated team of specialists, and it is governed throughout by enforced iteration budgets so the search converges rather than wanders. This is the deeper point: because such workflows are long-running and repeatedly executed, every run is also a chance to learn — and a system that learns from each execution compounds its engineering capability over time.

Headline result

AgentCore — headline result on ASAP7 7.5T, with no commercial EDA tools in the loop:

Acknowledgements

This work was made possible by the broader open-source hardware and EDA communities. The flow leveraged — and in places extended or modified — a range of open-source tools and components, including, to name just a few, the Yosys synthesis suite, the OpenROAD physical-design flow and its flow-scripts, the Verilator and Icarus Verilog simulators, the KLayout layout and DRC engine, an open RISC-V ISA reference simulator, the GNU compiler toolchain, and the ASAP7 predictive standard-cell library. We are grateful to the maintainers and contributors of these projects; this work builds on theirs rather than replacing it.

The chip is the proof; the workflow is the product

AgentCore is a real, sign-off-clean chip, and the trajectory that produced it climbed monotonically without a human at the wheel. But the result that matters is one level up: the same orchestration fabric, governed loops, provenance guarantees, and objective-agnostic closure machinery that produced this CPU generalize across design classes, nodes, and objective functions. As AI-assisted engineering becomes commonplace, the lasting edge will not come from any single automated task — it will come from an autonomous workforce whose long-running workflows get measurably better every time they run.