Case Studies
Real, end-to-end runs of Agentic Design Automation on chip-design workflows — the full story behind the numbers. Where a case study asks for your name and work email, one sign-up opens all of them.
Loop Engineering for Chip Design
In eight hours, an autonomous agentic loop found a XiangShan RISC-V configuration with +40% throughput, −28% power and −10% area vs. the expert-tuned reference.
Read the case study → June 2026 · Spec-to-GDSComposable Silicon
An autonomous multi-agent workforce takes a chip from spec to sign-off-clean GDS on a fully open-source flow — designing AgentCore, a 32-bit CPU, optimized for XLOPS/W with no human at the wheel.
Read the case study → June 2026 · Design VerificationCracking CVDP's Hardest Tasks
On CVDP's three Design Verification categories, Agentrys' self-learning agent lifts pass rates to 90–96% — a 4–15× improvement over prior state-of-the-art, with no human in the loop.
Read the case study → February 2026 · RTL CodingSelf-Improving Agents Solving CVDP RTL Coding Tasks
Agentrys achieves 95.8% overall pass rate on four RTL coding tasks of the Comprehensive Verilog Design Problems benchmark, including a perfect 100% on Code Debug, through seven generations of self-improving agents.
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